digital memories

• Negative-Resistance Read and Write Schemes for STT-MRAM in 0.13um CMOS, D. Halupka et al.,,International Solid State Circuits Conference (ISSCC) 2010


• Cross-coupled Bit-Line Biasing for 22-nm SRAM, D. Halupka and A. Sheikholeslami, International Conference on PhD Research in Microelectronics & Electronics 2009


• Method and apparatus for performing repeated content addressable memory searches, Robert N. McKenzie, Lawrence King and Richard Waterhouse, US Patent 7353330, April 2008


• Block programmable priority encoder in a CAM, Sean Lord, Robert McKenzie, Dieter Haerle, Steven Smith and Alan Roth, US Patent 7188211, March 1 2007


• Synchronous memory read data capture, Robert McKenzie and Peter Gillingham, US Patent application 11/477,659, June 2006


• Matchline Sense Circuit and Method, Peter Ma, Valerie Lines, Peter Gillingham, Robert McKenzie, Abdullah Ahmed and Stanley Jeh-Chun Ma, US Patent 6987682, January 1 2006


• Method and apparatus for an energy efficient operation of multiple processors in a memory, Duncan Elliott and Martin Snelgrove, US Patent 7,155,581, December 26 2006


• Method and apparatus for interconnecting Content Addressable Memories, Alan Roth, Robert McKenzie and Oswald Becca, US Patent 7062601, June 2006


• A 1GHz Embedded DRAM Macro and Fully Programmable BIST with At-Speed Bitmap Capability,Valerie Lines, Robert McKenzie, Hak June Oh, Hong Beom Pyeon, Matthew Dunn, Susan Palapar, Susan Coleman, Peter Nyasulu, Tony Mai, Seanna Pike, John McCready, Jody Defazio, Jin Ki Kim, Robert Penchuk, Zvika Greenfield, Fredy Lange, Alberto Mandler, Eric Jones and Matthew Silverstein, IEEE Memory Technology, Design & Testing Conference, August 2005


• Priority encoder circuit and method, Valerie L. Lines and Robert McKenzie, US Patent 6693814, February 12004


• Method and apparatus for wide word deletion in Content Addressable Memories, Robert McKenzie, Oswald Becca and Alan Roth, US Patent 7136961, November 2004


• Content addressable memory architecture, Dieter Haerle, Sean Lord and Robert N. McKenzie, US Patent 6775166, August 1 2004


• Advanced Ternary CAM circuits on 0.13um Logic Process Technology, Alan Roth, Richard C. Foss, Robert McKenzie and Doug Perry, IEEE Custom Integrated Circuits Conference, 2004


• Method and apparatus for an energy efficient operation of multiple processors in a memory, Duncan Elliott and Martin Snelgrove, US Patent 6560684, May 6 2003


• Memory device with multiple processors having parallel access to the same memory area, Duncan Elliott and Martin Snelgrove, US Patent 6,279,088, August 21 2001


• A 66 MHz, 2.3Mb Ternary Dynamic Content Addressable Memory, Valerie Lines, Abdullah Ahmed, Peter Ma, Stanley Ma, Robert McKenzie, Hong-Seok Kim and Cynthia Mar, August 2000


• Minimizing the effect of the host bus on the performance of a computational RAM logic-in-memory parallel-processing system, Peter Nyasulu, Ralph Mason, Martin Snelgrove and Duncan Elliott, IEEE Custom Integrated Circuits Conference , May 1999


• System design for a computational-RAM logic-in-memory parallel-processing machine, Peter M. Nyasulu, Carleton University, Carleton University, Adviser-Ralph Mason and Adviser-Martin Snelgrove, 1999


• Computational RAM: Implementing Processors in Memory, Duncan Elliott, Michael Stumm, Martin Snelgrove, Christian Cojocaru and Robert McKenzie, IEEE Design & Test of Computers, January 1999


• Memory device with multiple processors having parallel access to the same memory area, Duncan Elliott and Martin Snelgrove, US Patent 5956274, September 21 1999


• SIMD processor arrays for image and video processing: a review, Thinh Le, Martin Snelgrove and S. Panchanathan, Multimedia Hardware Architectures, 1998


• Architecture and Implementation of a Computational RAM Controller, Peter Nyasulu and Martin Snelgrove, Carleton University, 1998


• Computational RAM implementation of MPEG-2 for real-time encoding, Thinh Le, Martin Snelgrove and S. Panchanathan, Proc. SPIE Vol. 3021, Multimedia Hardware Architectures, February 8-14 1997


• A 1024 Processing-Element Computational RAM, Robert N. McKenzie, Martin Snelgrove and Duncan Elliott, TRIO, Kingston, May 1997


• Computing RAMs for media processing, Duncan Elliott, Martin Snelgrove, Christian Cojocaru and Michael Stumm, SPIE, SPIE Multimedia Hardware Architectures, February 8-14 1997


• Computational RAM: A Memory-SIMD Hybrid, Duncan Elliott, University of Toronto, 1997


• Computational RAM implementation of mean-average scalable vector quantization for real-time progressive image transmission, Thinh M. Le, S. Panchanathan and Martin Snelgrove, Proceedings of Canadian Conference on Electrical and Computer Engineering, 1996


• Method and apparatus for a single instruction operating multiple processors on a memory chip,Duncan Elliott and Martin Snelgrove, US Patent 5,546,343, August 13 1996


• (Do some) computing in RAM, Martin Snelgrove and Duncan Elliott, International Symposium on Future Information-Processing Technologies, Haikko, September 1995


• A Petaflop/s is Currently Feasible by Computing in RAM, Duncan Elliott, Martin Snelgrove, Christian Cojocaru and Michael Stumm, PetaFLOPS Frontier Workshop, February 1995


• Computational RAM: implementation and bit-parallel architecture, Christian Cojocaru, Carleton University,1995


• Computational RAM implementation of vector quantization for image compression, Thinh M. Le, Sethuraman Panchanathan and Martin Snelgrove, IEEE Conference on Visual Signal Processing and communications, Rutgers, NJ, Sep 19-20 1994


• An efficient synchronization mechanism for a multi-DSP application, Eugenia Distefano and Martin Snelgrove, ICSPAT, Nov 2-5 1992


• A synchronization mechanism for audio digital signal processing applications, Eugenia Distefano,University of Toronto, 1992


• Computational RAM: A Memory-SIMD Hybrid and its Application to DSP, Duncan Elliott, Martin Snelgrove and Michael Stumm, IEEE Custom Integrated Circuits Conference , May 3-6 1992


• Texture Mapping and Resampling for Computer Graphics, Robert Lansdale, University of Toronto, 1991


• A Hierarchical VLSI Design-Rule Checker on an MIMD Multiprocessor, Mark Moraes, University of Toronto, 1990


• Design and Implementation of a Global Ring for Hector, M. Mukhopadhyay, University of Toronto, 1990


• C* RAM: Memory with a Fast SIMD Processor, Duncan Elliott and Martin Snelgrove, CCVLSI, Oct 21-231990


• Optimal Hypertorus Configurations for Wafer-scale Multiprocessor Interconnection Networks, Carl Sommerfeldt, University of Toronto, 1990


• Shared virtual memory: a simple model for implementing distributed applications, Songnian Zhou, Thomas McInerny, Martin Snelgrove, Michael Stumm and David Wortman, ccece, Montreal, Sep 1989


• On interconnection networks for parallel processors, Ted H. Szymanski, University of Toronto, Co-Supervisor-V. C. Hamacher and Co-Supervisor-W. Martin Snelgrove, 1988


• Parallel standard cell placement algorithms with quality equivalent to simulated annealing, Jonathan S. Rose, Martin Snelgrove and Zvonko Vranesic, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1988


• Fast, high quality VLSI placement on an MIMD multiprocessor, Jonathan Rose, David R. Blythe, Martin Snelgrove and Zvonko G. Vranesic, International Conference on Computer Aided Design, Nov 10-13 1986


• Fast, high quality VLSI placement on an MIMD multiprocessor, Jonathan Rose, University of Toronto,1986


• Implementing the VASTOR architecture using a VLSI array of 1-bit processors, Tet H. Yeap, Wayne M. Loucks, Martin Snelgrove and Safwat Zaky, International Conference on Computer Design, Port Chester, Oct1985


• A multiprocessor fault simulator for VLSI circuits, Larry J. McNaughton, V. Carl Hamacher and Martin Snelgrove, CCVLSI, Toronto, Nov 1985


• VASTOR controller and its programming environment, Wai H. Lo, University of Toronto, 1984


• Design of a VASTOR processing element suitable for VLSI layout, Tet H. Yeap, University of Toronto,1984


• A VLSI implementation of a 1-bit processing element for the VASTOR array processor, Tet H. Yeap, Wai H. Lo, Martin Snelgrove, Wayne M. Loucks and Safwat Zaky, CCVLSI, Waterloo, Oct 1983


• A Vector Processor based on one-bit microprocessors, Wayne M. Loucks, Martin Snelgrove and Safwat Zaky, IEEE Micro, Feb 1982


• VASTOR: a microprocessor-based associative vector processor for small-scale applications, Wayne M. Loucks, Martin Snelgrove and Safwat Zaky, International Conference on Parallel Processing, Aug 1980

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